In transistor, a channel region in the semiconductor under the gate is doped with ions that are opposite to that of the source and drain. The operation of the transistor includes the application of applying a voltage to the gate. By varying the transverse electrical field, it is possible to control the current flow by modulating the longitudinal conductance of the channel. If the drain bias is applied such that source-body and drain-body junctions remain reverse-bias. A positive bias is applied to the gate of the NMOS, electrons will be attracted to the channel region, once enough electrons are drawn into the channel region by the positive gate voltage, the channel connects the source and the drain.
Thin film transistor (TFT) is a kind of a field effect transistor (FET). In typical FET, the source and drain and the channel region are formed in the substrate composed of single crystal silicon. The channel region of the TFT is different from the conventional FET. To phrase in another way, the channel region of the TFT is formed in a polysilicon or amorphous silicon layer on a substrate. For the application, the TFT can be used in flat panel display as switching transistors and in static random access memory as load devices. In order to form a quality SRAM, the TFT have to be decreased on off-current and increased the on-current. It is because that one of the important parameters to determine the performance is the drain off-set structure that is parts outside the gate electrode. The function of the off-set structure is similar to the lightly doped drain (LDD) structure in FET. The drain off-set structure can reduce the short channel effect or reduce punch-through effect caused by hot carrier and the structure also reduces the off-state leakage.
One of the approaches can be seen in U.S. Pat. No. 5,001,540 to Ishihara, he develops a dual gate TFT with off-set structure. The off-set region is the extension of a layer used to form the channel region. The dopant concentration is the same with that of channel region. Further, in the structure, the dimension of the off-set is determined by the width of the side walls spacers. FIG. 1 shows a further cross sectional view of a conventional polysilicon PMOS cell. In the cell, isolation structures composed of oxide 4 are formed in the substrate 2 for isolation. A driver NMOS is formed on the top of the substrate 2. A transistor 8 is located adjacent to the NMOS. A gate 10 isolated by dielectric material 6 is formed on the driver NMOS, and a polysilicon layer 10 is used to connect the driver NMOS and the doped region of the transistor 8. The gate 10 and the polysilicon layer 10 are composed of N type polysilicon. A P conductive type polysilicon layer 12 goes over the dielectric layer 6. A part of the layer 12 is implanted to define the source and drain. An off-set can be found adjacent to the drain. The separation between the source and drain defines the channel. The channel is oriented in a direction substantially parallel to the substrate, this leads to the conventional structure occupies a large cell area. It is not suitable to the trend of manufacture with high packing density. The channel formed of polysilicon provides smaller on-current compared to monocrystalline silicon channel.
Shepard provides a vertical dual gate thin film transistor, the article can be seen in U.S. Pat. No. 5,574,294. Shepard disclosed a self-aligned process for forming the source and drain regions in a dual gate TFT and further allows for the formation of off-set. Recently, some researches and developments have been approached to develop a vertical thin film transistor. The channel of the device is vertical to the surface of the substrate. Some arts provide a device cell with source, channel and drain that are vertically formed in a trench. The devices provide an advantage of higher density than others.
What is required is a TFT with a vertical cell structure to reduce the occupied area, thereby increasing the packing density.